This invention relates to methods of forming a pair of capacitors having a common capacitor electrode, to methods of forming DRAM circuitry, to integrated circuitry and to DRAM circuitry.
As DRAMs increase in memory cell density, there is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing cell area. Additionally, there is a continuing goal to further decrease cell area. One principal way of increasing cell capacitance is through cell structure techniques. Such techniques include three-dimensional cell capacitors, such as trenched or stacked capacitors. Yet as feature size continues to become smaller and smaller, development of improved materials for cell dielectrics as well as the cell structure are important. The feature size of 256 Mb DRAMs and beyond will be on the order of 0.25 micron or less, and conventional dielectrics such as SiO2 and Si3N4 might not be suitable because of small dielectric constants. Highly integrated memory devices, such as 256 Mbit DRAMs, are expected to require a very thin dielectric film for the 3-dimensional capacitor of cylindrically stacked or trench structures. To meet this requirement, the capacitor dielectric film thickness will be below 2.5 nm of SiO2 equivalent thickness.
Insulating inorganic metal oxide materials, such as ferroelectric materials or perovskite material or pentoxides such as tantalum pentoxide, have high dielectric constants and low leakage current which make them attractive as cell dielectric materials for high density DRAMs and non-volatile memories. Perovskite material and other ferroelectric materials exhibit a number of unique and interesting properties. One such property of a ferroelectric material is that it possesses a spontaneous polarization that can be reversed by an applied electric field. Specifically, these materials have a characteristic temperature, commonly referred to as the transition temperature, at which the material makes a structural phase change from a polar phase (ferroelectric) to a non-polar phase, typically called the paraelectric phase.
Preferred materials for the conductive capacitor electrodes when using these high k dielectric materials are Pt, Rh, Ru, Ir, and conductive oxides of these materials. Such materials are resistant to formation of insulative oxides which can otherwise undesirably form when many other conductive materials come in contact with, or during the processing to form, the high k dielectric materials.
In one type of DRAM circuitry, bit line contacts are made after formation of the array capacitors. In such event, provision is typically made to form bit contacts which extend through a capacitor cell plate layer without causing bit line to cell plate shorts. One way of accomplishing this objective is to first etch away regions of the cell plate layer and the capacitor dielectric layer where bit contacts will extend in a spaced manner through the cell plate layer. Subsequently, bit contact openings are etched in insulating material through these regions to lower substrate material. Subsequently, the bit contacts are filled with conductive material, and bit lines are ultimately formed. The high k capacitor dielectric materials and the conductive materials utilized therewith can be difficult materials to etch. Accordingly, etching conducted through the cell plate layer when utilizing such materials may not be complete, and undesirably leave material which effectively produces bit line to cell plate shorts.
The invention was principally motivated in addressing this particular problem, although the artisan will appreciate applicability of the invention in any other areas where pairs of capacitors are formed adjacent one another, and share a common capacitor plate.
This invention comprises a method of forming a pair of capacitors having a common capacitor electrode, a method of forming DRAM circuitry, and integrated circuitry and DRAM circuitry. In one implementation, a method of forming a pair of capacitors having a common capacitor electrode includes forming a pair of spaced first capacitor electrodes within insulating material. The first electrodes have uppermost surfaces which are below an uppermost surface of the insulating material. Some of the insulating material is removed about the first capacitor electrodes and a path is provided within the insulating material lower than its uppermost surface between the spaced first electrodes. A capacitor dielectric layer is formed over the first capacitor electrodes. A second capacitor electrode layer is formed over the capacitor dielectric layer common to the spaced first capacitor electrodes and within the path.
In one implementation, a method of forming DRAM circuitry includes forming an array of capacitor storage node electrodes over a substrate. A capacitor cell plate pattern is formed over the substrate. Conductive material is deposited over the substrate and into the capacitor cell plate pattern. The conductive material is polished outwardly of the pattern. In one implementation, a capacitor dielectric layer and a common cell plate layer are formed over the capacitor storage node electrodes. The cell plate layer is polished to form bit contact regions therethrough.
In one implementation, integrated circuitry comprises a pair of adjacent capacitors received within an insulative mass. The insulative mass having an outermost substantially planar surface extending at least partially between the adjacent capacitors. The capacitors respectively comprise a first capacitor electrode and a second capacitor electrode common to the pair. The second capacitor electrode has an outermost surface between the first capacitor electrodes which is elevationally coincident with or elevationally inward of the outermost substantially planar surface of the insulative mass. In one implementation, exemplary circuitry comprises DRAM.